A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

 
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< Input-output control apparatus, input-output control method, process control apparatus and process control method

> Memory card providing hardware acceleration for read operations

> Efficient resource mapping beyond installed memory space by analysis of boot target

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