The present invention comprises apparatus and a method for simultaneously programming multiple antifuses in a multiple tile field programmable gate array (FPGA). The invention comprises an FPGA having a plurality of logic modules with programmable elements. The logic modules are partitioned into a plurality of individually programmable groups and an isolation device may be coupled between the individually programmable groups of logic modules such that each of the programmable elements in each of the plurality of individually programmable logic modules may be programmed concurrently.

 
Web www.patentalert.com

< System and method for approximating intrinsic capacitance of an IC block

> Tuning programmable logic devices for low-power design implementation

> Digital television receiver and method of processing rating region table (RRT) including an extended version number field

~ 00527