A Direct Memory Access (DMA) system is provided for simplified communication between a processor and IP cores in an FPGA. The DMA system includes use of dual-port BRAM as a buffer and a decoder as a DMA control signal identification mechanism. The DMA control signals are stored in an area of the BRAM memory recognized by the decoder using chip enable (CE), write enable (WE), and address (ADR) signals. The decoder, upon recognizing a DMA control signal, will generate an event vector. The event vector triggers a READ operation by the receiving device at the associated BRAM control data memory address. DMA control codes can be detected as sent from either the processor or the IP core or both, depending upon whether the system employs a MASTER/SLAVE, SLAVE/MASTER, or PEER/PEER control model.