A memory arrangement includes an interface configured to transmit, code
and/or decode data in the form of data packets in accordance with a
predefined protocol. The memory arrangement includes at least two memory
banks, each memory bank including at least one memory cell. The memory
arrangement includes at least two memory-bank access devices configured
to facilitate accessing the data of the at least one memory cell of each
of the at least two memory banks. The memory arrangement includes at
least two temporary storage devices configured to temporarily store data
being transmitted between the interface and the at least two memory-bank
access devices. Each of the at least two temporary storage devices is
connected to the interface and to one of the at least two memory-bank
access devices.