A circuit design synthesis method is provided comprising: associating a
first cell library with a first block of a circuit design; associating a
second cell library with a second block of the circuit design; specifying
at least one constraint upon the overall circuit design; mapping a
portion of the first block to a cell in the first cell library based upon
the at least one constraint in view of a step of mapping a portion of the
second block to a cell in the second cell library; and mapping a portion
of the second block to a cell in the second cell library based upon the
at least one constraint in view of the step of mapping a portion of the
first block to a cell in the first cell library.