A system and method for efficiently performing bit-field extraction and
bit-field combination operations in a processor is provided. The system
includes a plurality of general purpose registers, a plurality of
predicate registers, and at least one execution unit configured to
extract a plurality of bit fields from a source reservoir and to populate
a plurality of destination lanes in response to a single instruction. In
addition, the execution unit is configured to write supplied fill data
into the source reservoir if the number of bits in the source reservoir
is less than a predetermined number. In addition or alternatively, the
system may include at least one execution unit configured to combine a
plurality of bit fields from a plurality of source lanes into a
continuous bit stream in response to a single instruction executable by
the processor.