Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is coupled to receive a second clock signal and the output signals from the first counting circuit. The second counting circuit generates output signals based on number of cycles of the second clock signal. A comparison circuit is coupled with to receive the output signals of the second counting circuit and to generate a reset signal if the output signals from the second counting circuit correspond to a pre-selected range.