A design analysis workstation for performing design analysis of integrated circuits provides facilities for extracting design and layout information from digital image-mosaics captured during deconstruction of an integrated circuit. The design analysis workstation enables propagation of signal information from an annotation object having a signal property to at least one connected annotation object in order to point to errors in the design analysis.

 
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< Multi-thread parallel segment scan simulation of chip element performance

> Apparatus and method for parity generation in a data-packing device

> Compact processor element for a scalable digital logic verification and emulation system

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