Timing analysis of integrated circuits fabricated in different Fabs is described. A first speed file and a second speed file for a type of integrated circuit respectively fabricated in a first Fab and a second Fab are generated, the first speed file and the second speed file having corresponding types of delays. At least a portion of the corresponding types of delays have different delay values. A circuit design using the first speed file is compiled. The circuit design is for instantiation in programmable logic of the type of integrated circuit. The method further includes checking whether the circuit design as compiled using the first speed file passes timing constraints of the circuit design using the first speed file and checking whether the circuit design as compiled using the first speed file passes the timing constraints of the circuit design using the second speed file.