A memory system having a memory controller and a daisy chain of memory
chips. The memory controller is coupled to memory chips in the daisy
chain of memory chips by an address/command bus chain. The memory
controller is coupled to memory chips in the daisy chain of memory chips
by a data bus chain having a number of data bus bits. The data bus chain
has a first portion of data bus bits dedicated to transmitting write data
from the memory controller to a memory chip. The data bus chain has a
second portion of data bus bits dedicated to transmitting read data from
a memory chip to the memory controller. Apportionment of data bus bits
between the first portion and the second portion is programmable.
Programming is done by pin connection, scanning of a value, or by request
from a processor coupled to the memory controller.