A plasma display panel includes an upper substrate; an upper dielectric layer formed on a lower surface of the upper substrate; a lower substrate facing the upper substrate; a lower dielectric layer formed on an upper surface of the lower substrate; a plurality of address electrodes disposed in the lower dielectric layer and separated from each other; a plurality of barrier ribs, including longitudinal barrier ribs that extend between and parallel to the address electrodes and separated from each other, disposed between the upper substrate and the lower substrate; a phosphor layer formed in discharge spaces disposed between the longitudinal barrier ribs; and a plurality of pairs of sustain electrodes disposed in the upper dielectric layer, each of the pairs including: a first sustain electrode and a second sustain electrode protruding outward respectively from the adjacent longitudinal barrier ribs over the discharge space disposed between them to discharge gap.