Mechanisms for asynchronous clock modeling in an integrated circuit simulation are provided. The mechanisms of the illustrative embodiments provide clock skewing logic for phase shifting a clock signal in an integrated circuit design. This clock skewing logic adds delay to one or more clocks of an integrated circuit design to thereby place that clock out of phase with other clocks in the integrated circuit design. In one illustrative embodiment, delay is introduced into a clock net in an increasing manner with each enablement of the clock skewing logic. In another illustrative embodiment, the introduced delay is increased and decreased within a window from no phase shift of the clock net up to a maximum phase shift of the clock net. Once the maximum phase shift is reached, the amount of delay introduced is decreased with subsequent enablement of the clock skewing logic.