The method includes forming a 1-10000 nm thick SiO.sub.2, HfO.sub.2, Al.sub.2O.sub.3 and/or quartz gate dielectric on an Si back gate. An Al or Mo gate electrode is formed on the gate dielectric. An Al.sub.2O.sub.3 insulating layer is formed over the gate electrode. A C, Si, GaAs, InP, and/or InGaAs nanotube is formed on the insulating layer and gate dielectric. The nanotube has a central region on the insulating layer above the gate electrode and first and second ends on the gate dielectric. A source is formed on the first end and spaced from the central region and gate electrode by a first peripheral region. A drain is formed on the second end and spaced from the central region and gate electrode by a second peripheral region. The first and second peripheral regions are doped with Cl.sub.2, Br.sub.2, K, Na, or a molecule of polyethylenimine using wet deposition or evaporation.