An architecture is provided for implementing bypass, repeater and retimer
functions in high-speed multi-port SERDES bypass ports and devices.
Specifically, this architecture uses clock recovery to implement a
repeater function which retransmits data synchronously at a
recovered-clock rate, providing very low-latency as no elastic-buffers
are required to perform clock-rate compensation. It also supports a full
retiming function where incoming data is retransmitted synchronously to
the local-clock domain, in which case elastic-buffers are needed to
compensate for differences between incoming clock and local-clock
domains. The architecture disclosed herein is advantageously used for
Fibre-Channel Arbitrated Loop (FCAL) applications. It can also be
leveraged in other applications like Infiniband, XAUI, PCI-Express to
create a single device that be used as "eye-opener" to extend reach with
low-latency when operated in "repeater mode" and as retiming device when
operated as "retimer-mode". It can also perform as an amplifier with very
low-latency when operated in bypass-mode.