The present invention generally relates to memory controllers operating in
a system containing a variable system clock. The memory controller may
exchange data with a processor operating at a variable processor clock
frequency. However the memory controller may perform memory accesses at a
constant memory clock frequency. Asynchronous buffers may be provided to
transfer data across the variable and constant clock domains. To prevent
read buffer overflow while switching to a lower processor clock
frequency, the memory controller may quiesce the memory sequencers and
pace read data from the sequencers at a slower rate. To prevent write
data under runs, the memory controller's data flow logic may perform
handshaking to ensure that write data is completely received in the
buffer before performing a write access.