A test method and apparatus for a semiconductor memory device is characterized by the sequentially programmed use of two test different modes. A first test mode tests at least signal line integrity for the semiconductor memory device by testing a merged set of bits line. The second test mode further tests at least signal line integrity after first separating the merged bits lines. Logical combination of test data derived from the first and second test modes are used to generate error detection signals. At least one bit line associated with a parity bit is preferable merged and separated in the foregoing approach.

 
Web www.patentalert.com

< Arrangement for the optical detection of light radiation which is excited and/or backscattered in a specimen with a double-objective arrangement

> Method for correlating spectroscopic measurements with digital images of contrast enhanced tissue

~ 00483