An FPGA system includes a combined shift register and look up table (LUT)
forming a shift register LUT (SRL) that provides data write, reset and
shift enable on a cell-by-cell basis. The data write and reset can be
performed during FPGA operation without requiring a number of frames or
columns of configuration memory cells to be reprogrammed, as with
conventional SRAM cells. The shift enable provides for synchronization to
facilitate the cell-by-cell write and reset.