A method is provided, wherein a virtual internal master clock is used in
connection with a RISC CPU. The RISC CPU comprises a number of
concurrently operating function units, wherein each unit runs according
to its own clocks, including multiple-stage totally unsynchronized
clocks, in order to process a stream of instructions. The method includes
the steps of generating a virtual model master clock having a clock
cycle, and initializing each of the function units at the beginning of
respectively corresponding processing cycles. The method further includes
operating each function unit during a respectively corresponding
processing cycle to carry out a task with respect to one of the
instructions, in order to produce a result. Respective results are all
evaluated in synchronization, by means of the master clock. This enables
the instruction processing operation to be modeled using a sequential
computer language, such as C or C++.