Verifying a process margin for a mask pattern includes receiving the mask pattern for patterning features on a semiconductor wafer. The mask pattern is modified according to a wafer pattern model operable to estimate a wafer pattern resulting from the mask pattern. An intermediate stage model is selected to apply to a portion of the mask pattern, where the intermediate stage model is operable to estimate an intermediate stage of the wafer pattern. A process margin of the portion is verified by selecting a test of the intermediate stage model, and performing the test on the portion to verify the process margin of the portion.

 
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