A NAND flash memory device and method of manufacturing the same is
disclosed. Source and drain select transistor gates are recessed lower
than an active region of a semiconductor substrate. A valid channel
length of the source and drain select transistor gates is longer than a
channel length of memory cell gates. Accordingly, an electric field
between a source region and a drain region of the select transistor can
be reduced. It is thus possible to prevent program disturbance from
occurring in edge memory cells adjacent to the source and drain select
transistors in non-selected cell strings.