A semiconductor substrate has a cell region and a peripheral circuit
region surrounding the cell region. In the cell region a plurality of
lower electrodes are connected to a conductive region of the
semiconductor substrate, and are arrayed along row and column directions.
A dielectric layer is formed on the plurality of lower electrodes. An
upper electrode is formed on the dielectric layer, entirely covering the
cell region, and is formed extending to a portion of the peripheral
circuit region that has a step coverage lower by a height of the lower
electrode than the cell region. An edge of the upper electrode has
square-shaped projections that are distanced from each other at a uniform
interval and are repetitively arrayed. With the described structure,
pattern defects can be sensed and controlled, preventing and
substantially reducing process defect.