A method for coding a sequence of data bits (B1-B5), at least one of said bits having a logical on value or a logical off value. The data bits are organized in a sequence of time slot frames (Fr1-FR5). At least one time slot frame has a plurality of time slots (ZS11-ZS13). Each of the plurality of times slots are capable of having an on value or an off value (Z1 or Z0). The coding comprises preloading a time slot (ZS14, AF) from the plurality of time slots with an off value (Z0). Each of the time slots (ZS11-ZS13) other than the preloaded time slot (ZS14) are loaded with an on value or an off value to form a logical on value or logical off value for the at least one of said data bits. A time slot with an off value from the plurality of time slots always follows another time slot with an on value from the plurality of time slots. The logical on value is complementary to the logical off value.

 
Web www.patentalert.com

< Reconfigurable linear sensor arrays for reduced channel count

> System and method for GPU acceleration of push-relabel algorithm on grinds

~ 00472