An integrated device for sampling data packets asserted sequentially on a
system bus, including a clock input for receiving a bus clock signal, a
data bus interface for receiving the data packets and for detecting at
least one data strobe indicating data validity, and dynamic source
synchronized sampling adjust logic. The dynamic source synchronized
sampling adjust logic includes sampling logic which selects and latches
each data packet in response to the data strobe and which provides
latched data packets, and select logic which selects from among the
latched data packets based on a read pointer. A method of sampling data
packets asserted sequentially on a data bus for one or more bus clock
cycles including detecting operative edges of a data strobe, selecting a
data packet for each detected operative edge, and latching each selected
data packet.