A method for testing at least one logic block of a processor includes,
during execution of a user application by the processor, the processor
generating a stop and test indicator. In response to the generation of
the stop and test indicator, stopping the execution of the user
application and, if necessary, saving a state of the at least one logic
block of the processor. The method further includes applying a test
stimulus for testing the at least one logic block of the processor. The
test stimulus may be shifted into scan chains so as to perform scan
testing of the processor during normal operation, such as during
execution of a user application.