A circuit provides the widest possible window for capturing data and
preventing run-through in a FIFO register. The FIFO register includes two
registers per I/O. Two FIFO input clocks are used, one for each FIFO
register. When one FIFO clock is active, the other is automatically
disabled. Initially, the circuit is reset such that one clock is active,
and the other disabled. Upon receiving a valid READ command, a shift
chain attached to the FICLK that is currently low begins counting the
clock cycles. This eventually determines when the FICLK that is currently
low can be enabled. The final enable is dependent upon the turning off
the FICLK that is currently high. The FICLK that is enabled during the
reset turns off a fixed delay after the falling edge of the YCLK
associated with the READ command.