A sampling circuit and method are disclosed. The sampling circuit includes
a buffer, a holding capacitor, a set of switches, and at least two
voltage references. The buffer drives buffered analog input signal via a
first switch to a first node of holding capacitor. A second switch
connects a second node of the holding capacitor to a first reference
voltage. A third switch connects the second node of the holding capacitor
to a second reference voltage. When the first and second switches are
closed, charge accumulates on the holding capacitor. Opening the second
switch terminates charging. The third switch biases the charged capacitor
to the second reference voltage and the sampled output is taken from the
first node of the holding capacitor. A rotary clock and control circuit
provide the precise timing for the switches, especially the opening of
the second switch, which determines the end of the sampling time.