Methods and apparatus to test memories, such as, for example, caches of processors, are disclosed. In one aspect, an apparatus may include a pseudo random address generation unit, such as, for example, including a linear feedback shift register, to generate pseudo random memory addresses, and a deterministic data generation unit, such as, for example, including a state machine, to generate deterministic data to be written to the pseudo random memory addresses. Computer systems and other electronic systems including such apparatus are also disclosed.