A clock selector for selecting a set of candidate clock signals from among a plurality of input clock signals. The phase selector includes control logic adapted to generate a plurality of control signals and a plurality of muxes controlled by the control signals and arranged in two or more stages having at least a first stage and a last stage. The input to the first stage is the plurality of input clock signals. At least one stage is adapted to (i) receive a plurality of clock signals, (ii) drop at least the first or the last clock signal of the received plurality of clock signals, and (iii) output a reduced plurality of clock signals. The output of the last stage is the set of candidate clock signals.