A single instruction, multiple data (SIMD) processor including a plurality
of addressing register sets, used to flexibly calculate effective operand
source and destination memory addresses is disclosed. Two or more address
generators calculate effective addresses using the register sets. Each
register set includes a pointer register, and a scale register. An
address generator forms effective addresses from a selected register
set's pointer register and scale register; and an offset. For example,
the effective memory address may be formed by multiplying the scale value
by an offset value and summing the pointer and the scale value multiplied
by the offset value.