A shift register capable of supplying only a necessary clock signal to a necessary unit register with simple constitution. A semiconductor device is provided with a shift register in which a plurality of stages of unit registers is connected, in which the unit register comprises a flip-flop circuit, a first switch and a second switch, a first clock signal line is electrically connected to the flip-flop circuit through the first switch, a second clock signal line is electrically connected to the flip-flop circuit through the second switch, the first switch is controlled to be on/off by an output signal from the flip-flop circuit, and the second switch is controlled to be on/off by an input signal to the flip-flop circuit.