A controller and one or more intermediate devices that are connected to a plurality of processors and this controller so that communications are possible are provided. A first access message including a designated value designated by the processor is transmitted to the controller by a first intermediate device connected to the processor. The controller specifies a local memory address corresponding to the designated value included in the first access message, and transmits a second access message including this specified local memory address to two or more other processors. The two or more other processors or second intermediate devices that are connected to these processors access local memory regions of two or more local memories respectively corresponding to two or more other processors, which are local memory regions corresponding to the local memory addresses included in the second access message.