To provide a semiconductor memory device comprising a phase-change memory and having high compatibility with DRAM interface. The memory cell array 18 comprises a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register 15 and a data register 14 respectively, and a write operation is not performed on the memory cell array 18 in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array 18. At this time, two write cycles--RESET cycle and SET cycle--are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).