The present invention relates to a self-aligning patterning method which
can be used to manufacture a plurality of multi-layer thin film
transistors on a substrate.The method comprises firstly forming a
patterned mask 20 on the surface of a sacrificial layer 18 which is part
of a multi-layer structure 10 which comprises the substrate 12, a
conductive layer 14, an insulating layer 16 and the sacrificial layer 18.
Unpatterned areas are then etched to remove the corresponding areas of
the sacrificial layer, the insulating layer 16 and the conductive layer
14 thereby leaving voids. A layer of dielectric 22 is then deposited over
the etched multi-layer structure to at least substantially fill the
voids. The deposited dielectric is then etched in order to at least
partially expose the sides of the remaining areas 28 of the sacrificial
layer. Conductive material 30 is then deposited on the surface of the
etched dielectric. Finally, the remaining areas 28 of the sacrificial
layer are removed together with any overlying material.The resulting
plurality of multi-layer thin film transistors is preferably in the form
of an array which may in turn be formed into a display device by coupling
each transistor in the array to a light-emitting cell.