A process is described for semiconductor device integration at chip level
or wafer level, in which vertical connections are formed through a
substrate. A metallized feature is formed in the top surface of a
substrate, and a handling plate is attached to the substrate. The
substrate is then thinned at the bottom surface thereof to expose the
bottom of the feature, to form a conducting through-via. The substrate
may comprise a chip having a device (e.g. DRAM) fabricated therein. The
process therefore permits vertical integration with a second chip (e.g. a
PE chip). The plate may be a wafer attached to the substrate using a
vertical stud/via interconnection. The substrate and plate may each have
devices fabricated therein, so that the process provides vertical
wafer-level integration of the devices.