A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.

 
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> D/A converter for a digital signal after non-linear A/D conversion, audio signal processing circuit and liquid crystal display device including the same

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