A system includes a processor and a size bounded first-in first-out (FIFO)
memory that is connected to the processor and a display is connected to
the processor. A managing process to run on the processor to manage the
FIFO memory structure. The FIFO memory includes a counter portion and a
value portion for each of a tail portion and a head portion, and the
managing process is non-blocking. The counter portion is used as a
timestamp to maintain FIFO order.