A system and method for collecting and analyzing integrated circuit test vehicle test data by identifying various blocks of circuitry through at least two different intersecting test paths. In one embodiment, the process test circuits may be arranged in a matrix format and connected so that they may be tested along rows or columns. When a failure along a specific row and a specific column is identified, the process test circuit at the intersection may be identified as the failure point.

 
Web www.patentalert.com

< Bump-on-lead flip chip interconnection

> Method for determining the arrangement of contact areas on the active top side of a semiconductor chip

~ 00430