A method for analyzing a circuit design identifies a possible noise fault for a timing interval based on a timing analysis of a victim net and at least one aggressor net of the circuit design and determines whether the noise fault is feasible based on a behavioral representation of the victim net and the aggressor net for the timing interval.

 
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< System for at-speed automated testing of high serial pin count multiple gigabit per second devices

> Printing a mask with maximum possible process window through adjustment of the source distribution

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