A counter circuit includes a counter section having flip-flops of a plurality of stages. The flip-flops from a first stage to an (N-1).sup.th (N is an integer more than 2) stage synchronously count a clock signal. A mask circuit section controls supply of the clock signal to the flip-flop of an N stage based on outputs of the flip-flops from the first stage to the (N-1).sup.th stage.