A multi-block SRAM memory system is described where a single global clock
pulse is distributed to each memory block from the central control. At
each SRAM memory block a local signal generator uses the globally
distributed clock pulse to generate the required memory control pulse
signals. By generating the memory control pulses locally, instead of
distributing these from the central control the variations in skew are
greatly reduced. Thus the required timing relationship between memory
control signals can be achieved with smaller timing margins. This allows
higher speed memory cycle and more reliable memory operation.