A method and apparatus for synthesizing high-frequency signals, such as
wireless communication signals, includes a phase-locked loop (PLL)
frequency synthesizer with a variable capacitance voltage controlled
oscillator (VCO) that has a discretely variable capacitance in
conjunction with a continuously variable capacitance. The discretely
variable capacitance may provide coarse tuning adjustment of the variable
capacitance to compensate for capacitor and inductor tolerances and to
adjust the output frequency to be near the desired frequency output. The
continuously variable capacitance may provide a fine tuning adjustment of
the variable capacitance to focus the output frequency to match precisely
the desired frequency output. During fine tuning adjustment, the PLL may
be controlled by a plurality of analog control signals. The analog
control signals may be derived by first generating a plurality of phase
shifted signals from a divided version of the VCO output clock. Second,
the phase differences between the plurality of phase shifted signals and
a divided version of a reference clock may be detected and then converted
to the analog control signals.