In order to output an active command to an SDRAM, at time t0, output of a valid row address starts and a control signal ras# enters the active state. Thereafter, a control signal cs# enters the active state at time t1. At time t3, the signal cs# returns to the negative state. At time t4 when some period of time has passed after time t3, output of the valid row address stops and the signal ras# enters the negative state. Outputs of the address signal adr and the control signals ras#, cas# and we# are controlled in synchronization with a modulated clock S-clk, which is generated at the spread spectrum generator. This reduces the electromagnetic interference that is caused by the address signal adr and the control signals ras#, cas# and we#.