This method for decoupling capacitance analysis improves upon existing
techniques to attempt to give a more accurate representation of the power
supply fluctuations on a chip while keeping runtime comparable. This
method employs the following techniques; a) a method for descending
through hierarchy and dividing the design into a variable sized grid; b)
an algorithm to determine which grid locations of a design don't have
enough decoupling capacitors for all of the devices in that grid
location; c) an algorithm to determine which grid locations are subject
to harmful neighboring effects; and d) a method to display the results of
the calculations in a graphical manor to allow easy identification of
problem areas.