In some embodiments an apparatus and method may comprise a plurality of
lanes between two clock domains, each lane comprising circuitry to
generate a first signal when the lane may lose cycle coherency with other
of the plurality of lanes, generate a second signal to signify a lane has
been delayed, and a control circuit coupled with the plurality of lanes
to add latency only to lanes that did not generate a second signal if the
control circuit detects a first signal from any of the plurality of
lanes.