A highly economical alterable ASIC implements partitioned segments of an ASIC design in a smaller Silicon foot-print, each segment utilizing the entire IC. The device is able to switch quickly between the multiple segments with global control signals, without incurring long delays to reconfigure configuration memory. The alterable ASIC comprises programmable logic blocks and a configuration circuit with multiple sets of configuration memory, each set programmed to hold an optimized segment. Either random access memory (RAM) or mask configured read only memory (ROM) store the partitioned segments.