A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plurality of transistors. A second global bitline may be connected to a second one of the plurality of transistors. A secondary sense amplifier may be connected to the first and second global bitlines.

 
Web www.patentalert.com

< Methods for generating a reference voltage and for reading a memory cell and circuit configurations implementing the methods

> Single transistor sensing and double transistor sensing for flash memory

~ 00417