In case an input voltage is zero, to sufficiently shut off an output current, a source side of a first transistor T1 is connected to the drains of fourth and fifth transistors T4 and T5, and during a self-bias period of the first transistor T1, a source of the first transistor T1 is made a second potential through the fourth transistor T4, and in a gate potential setting period of the first transistor T1 by an input voltage Vin after the completion of the self-bias period, the source of the first transistor T1 is made a third potential through the fifth transistor T5.