An apparatus, method, and computer-readable media that provide fast and accurate prediction of the hardware cost of logic to extend a processor. Aspects of the invention enable designers to explore instruction set alternatives at the architectural level without completing a lengthy implementation flow. Embodiments may use existing standard cell libraries and EDA tools to obtain the cost of parameterized building blocks, to build components of a microprocessor such as instruction decoder, register files, and data path execution units. The cost of an application specific microprocessor is derived from the cost of each of its structural components.