A power (voltage) switching circuit in a semiconductor memory device, capable of reducing leakage current in a standby mode of operation and shortening the wake-up time when a standby mode is switched to an operation mode. The power (voltage) switching circuit comprises a first power switch, a second power switch, and a third power switch operatively connected to at least one bitline in a memory cell array, configured to selectively output, as a cell power voltage, a dynamically selected one of a first power supply voltage, a second power supply voltage, and a third power supply voltage, respectively in response to a first, second or third applied switch control signals. The second power supply voltage being higher than the first power supply voltage and, the third power supply voltage being lower than the first power supply voltage. A cell power control unit controls states of the first, second and third switch control signals so that the cell power voltage is applied as the third (lowest) power supply voltage in a standby state and that when the standby state is switched to an operating state the cell power voltage is supplied as the second (highest) power supply voltage during a predefined period of time and then as the first power supply voltage.