A method of producing a layout representation corresponding to an
integrated circuit (IC) device design can include generating an initial
layout representation in accordance with a predetermined set of design
rules and simulating how structures within the initial layout
representation will pattern on a wafer. Based on the simulation, portions
of the layout representation, which include structures demonstrating poor
manufacturability and/or portions of the layout representation in which
extra manufacturability margin is present, can be identified. Portions of
the layout representation including structures demonstrating poor
manufacturability and/or in which extra manufacturability margin is
present can be modified to optimize the layout representation.